In integrated circuits, different sections of the design are often required to operate at differing voltages, either permanently or on a variable basis. For example, input and output drivers of silicon chips often require 1.8V, 2.5V, or 3.3V signalling whereas the core voltage for the main circuitry operates at a lower voltage, such as 1.0V. To transfer logical signals between these different voltage domains, a level shifter circuit is required. This circuit takes an input signal at voltage Y and translates it to an output signal at voltage X, where X>Y for a low-to-high level shifter, and X<Y for a high-to-low level shifter.
Power consumption of silicon chips is in many applications the most important design metric to consider, and is increasingly becoming important in all areas of chip design. The most effective way of reducing power in a silicon chip is to reduce the supply voltage, since power dissipation is proportional to the cube of supply voltage. Thus, a very low power chip will ideally operate with a very low power supply.
The power supply for the inputs and outputs (I/Os), and various other minor sections of the chip (such as the PLL), are generally fixed. It is predominantly the core voltage, powering most of the high speed transistors on the die, which can be reduced, and which gives the greatest benefit.
Many timing paths on chip, and to/from the chip's I/Os, are critical, and as such it is important that the operation of the level shifter be as fast as possible. Certainly, some applications are not sensitive to speed, however many of them are sensitive and require good performance.
It is also important to keep the implementation of the level shifter simple (in terms of the amount of logic required). For example, a design which requires many intermediate supply domains to translate into during the course of the very low to high voltage level shift will not only be slow, but will also be more complex, as those additional intermediate power domains will need to be routed to all level shifters, maintain good supply integrity, etc. For example, it is preferable to level shift directly from 0.5V to 2.5V without having to go through intermediate voltage levels such as 0.5V to 1.0V to 2.5V, or 0.5V to 1.0V to 1.8V to 2.5V, as these latter solutions would be more complex to implement, and are slow.
Thus, it would be advantageous to have a simple, high speed level shifter implementation which successfully translates between extremely low voltage and high voltage domains.
The implementation of a level shifter to translate from a high voltage down to a very low voltage is relatively trivial. Many suitable circuits are available for this, typically involving NMOS-only pull up/down cascode stacks with cross-coupled PMOS headers, and some buffers.
It is the implementation of a simple high speed level shifter from a lower to a higher voltage domain which poses the greatest difficulty, and for which this invention applies.